This invention relates to a tunnel transistor.
A tunnel transistor is described, for example, in a letter contributed by Sanjay Banerjee and three others to the IEEE Electron Device Letters, Volume EDL-8, No. 8 (August 1987), pages 347 to 349, under the title of "A New Three-Terminal Tunnel Device". In the tunnel transistor according to Banerjee et al, positive use is made of a tunnel effect which gives rise to problems when MOS (metal-oxide-semiconductor) FET's (field effect transistors) are scaled down to a submicron order. It is therefore possible to implement such tunnel transistors as a highly integrated semiconductor circuit.
In the manner which will later be described a little more in detail, the Banerjee et al tunnel transistor comprises a semiconductor substrate having a principal surface and doped with an impurity of a first conductivity type to a relatively lower concentration. First and second degenerate semiconductor layers are formed contiguous to the principal surface with a spacer region left therebetween in the substrate. The first (degenerate) semiconductor layer is doped with an impurity of the first conductivity type to a higher concentration. The second (degenerate) semiconductor layer is doped with an impurity of a second conductivity type opposite to the first conductivity type to the higher concentration. An insulating film is formed on the principal surface to cover the first semiconductor layer and the spacer region and partly the second semiconductor layer, leaving a major portion of the second semiconductor layer uncovered. The principal surface is left exposed around the insulating film as an exposed surface. A source electrode is formed on the exposed surface adjacent to the first semiconductor layer. A drain electrode is formed on the major portion of the second semiconductor layer. A gate electrode is formed on the insulating film. For the reason which will become clear later in the description, the insulating film is herein called a gate isolating or spacing film.
Although effective in highly integrating such tunnel transistors, the Banerjee et al tunnel transistor can still be improved to provide a larger tunnelling current. Furthermore, it is possible to give a higher speed to operation of the tunnel transistor.